Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
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ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
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Proceedings of the 27th annual international symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Spider: A High-Speed Network Interconnect
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Variability in Architectural Simulations of Multi-Threaded Workloads
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Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
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HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
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Proceedings of the 32nd annual international symposium on Computer Architecture
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Proceedings of the 32nd annual international symposium on Computer Architecture
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IEEE Design & Test
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GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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Proceedings of the 33rd annual international symposium on Computer Architecture
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ASR: Adaptive Selective Replication for CMP Caches
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HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
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Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the Conference on Design, Automation and Test in Europe
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
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Proceedings of the 38th annual international symposium on Computer architecture
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
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Proceedings of the 39th Annual International Symposium on Computer Architecture
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Microprocessors & Microsystems
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With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging. In this article, we explore the architectural-level implications of interconnection network design for CMPs with up to 128 fine-grain multithreaded cores. We evaluate and compare different network topologies using accurate simulation of the full chip, including the memory hierarchy and interconnect, and using a diverse set of scientific and engineering workloads. We find that the interconnect has a large impact on performance, as it is responsible for 60% to 75% of the miss latency. Latency, and not bandwidth, is the primary performance constraint, since, even with many threads per core and workloads with high miss rates, networks with enough bandwidth can be efficiently implemented for the system scales we consider. From the topologies we study, the flattened butterfly consistently outperforms the mesh and fat tree on all workloads, leading to performance advantages of up to 22%. We also show that considering interconnect and memory hierarchy together when designing large-scale CMPs is crucial, and neglecting either of the two can lead to incorrect conclusions. Finally, the effect of the interconnect on overall performance becomes more important as the number of cores increases, making interconnection choices especially critical when scaling up.