Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Digital systems engineering
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Implementation analysis of NoC: a MPSoC trace-driven approach
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
NoC Topologies Exploration based on Mapping and Simulation Models
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Flattened Butterfly Topology for On-Chip Networks
IEEE Computer Architecture Letters
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Clock distribution scheme using coplanar transmission lines
Proceedings of the conference on Design, automation and test in Europe
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
A PLL Design based on a Standing Wave Resonant Oscillator
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
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Most network-on-chip (NoC) architectures are based on a mesh-based interconnection structure. In this paper, we present a new NoC architecture, which relies on source synchronous data transfer over a ring. The source synchronous ring data is clocked by a resonant clock, which operates significantly faster than individual processors that are served by the ring. This allows us to significantly improve the cross section bandwidth and the latency of the NoC. We have validated the design using a 22nm predictive process. Compared to the state-of-the-art mesh based NoC, our scheme achieves a 4.5× better bandwidth, 7.4× better contention free latency with 11% lower area and 35% lower power.