Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A PLL Design based on a Standing Wave Resonant Oscillator
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
PEEC based parasitic modeling for power analysis on custom rotary rings
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Implementing digital logic with sinusoidal supplies
Proceedings of the Conference on Design, Automation and Test in Europe
Synchronization scheme for brick-based rotary oscillator arrays
Proceedings of the great lakes symposium on VLSI
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
A source-synchronous Htree-based network-on-chip
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Rotary traveling wave oscillator frequency division at nanoscale technologies
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Proceedings of the Conference on Design, Automation and Test in Europe
ZeROA: zero clock skew rotary oscillatory array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signaling in the Gigahertz range (we are able to achieve clock rates of 8GHz and above). The clock is transported as an oscillatory wave on a pair of conductors. An oscillatory standing wave is formed across a transmission line loop, which is connected beginning-to-end through a Mobius configuration. A single cross coupled inverter pair is required to maintain oscillation across the ring. The design is aimed to achieve low skew, low power and extreme high frequency global clock situations. The energy recycling nature of a standing wave along a transmission line allows us to keep very high frequencies oscillations along a conductor with almost no power consumption at all. A special wide input range driver was designed to convert the differential signals on the coplanar transmission lines into a square clock pulse for standard clock sinks. The design uses CMOS 90nm BSim3v model cards for all simulations, with the transmission lines implemented on Metal8.