Signal Integrity - Simplified
Power Analysis of Rotary Clock
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling, optimization and control of rotary traveling-wave oscillator
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Clock distribution scheme using coplanar transmission lines
Proceedings of the conference on Design, automation and test in Europe
Zero clock skew synchronization with rotary clocking technology
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
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Resonant rotary clocking is a low power-high speed clock distribution technology for the modern VLSI circuits. Alternative topological implementations of rotary clocking with non-regular custom rings have been proposed in literature. In this paper, the impact of parasitics of the non-regular topological geometries on the rotary operating characteristics is presented. In particular, partial element equivalent circuit (PEEC) analysis is used to show that the corner geometry in a custom ring increases the mutual inductance approximately by 80%. Also, SPICE simulations are performed where the parasitics due to the topological factors are incorporated for an 8% increased accuracy in simulation. Further, the power dissipation on the rotary ring is analyzed with varying number of corners. When tested with the IBM R1-R5 benchmark circuits, the total power dissipated on a custom ring (corners between 4 and 12) is within ±5% of the total power dissipated on a regular ring(4 corners).