FACET: a CAE system for RF analogue simulation including layout
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
Impact of Technology Scaling in the Clock System Power
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Inductance calculations in a complex integrated circuit environment
IBM Journal of Research and Development
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling, optimization and control of rotary traveling-wave oscillator
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PEEC based parasitic modeling for power analysis on custom rotary rings
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Proceedings of the Conference on Design, Automation and Test in Europe
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Rotary clock is a multi-gigahertz clock distribution technique based on the principle of wave propagation in transmission lines. In this paper, we perform the first quantitative investigation on the power dissipation of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from a layout specification of a rotary clock design. As a result, we are able to accurately estimate the frequency and power dissipation of the rotary clock design using SPICE simulations. Using our tool, we have uncovered the key power dissipation mechanisms of rotary clock and proposed several power reduction strategies. Furthermore, our power analysis has revealed that rotary clock designs can achieve power savings of up to 70% in comparison with conventional clock tree implementations.