IEEE Transactions on Computers
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
Design of Resonant Global Clock Distributions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power Analysis of Rotary Clock
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Sensitivity evaluation of global resonant H-tree clock distribution networks
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design of rotary clock based circuits
Proceedings of the 44th annual Design Automation Conference
Design methodology for global resonant H-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power rotary clock array design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Library-aware resonant clock synthesis (LARCS)
Proceedings of the 49th Annual Design Automation Conference
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Increasing demands on computing power have spurred the development of faster, higher-density Integrated Circuits (ICs), compounding power and complexity concerns in design budgets. The clock distribution network is a significant contributor to such power and complexity concerns. Resonant rotary clocking is a relatively new technology that realizes several benefits over current clocking methods, including power, frequency, and variation tolerance, yet lacks the automation tools to promote increased use. Towards this end, an automated rotary clock routing methodology is presented that generates custom topology rotary ring routes with tree subnetworks. In addition to the benefits of adiabatic clocking, the presented custom topology router permits 38.6% shorter wirelengths on average for register tapping, compared to traditional prescribed skew, binary tree routing.