Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Clock Distribution Using Cooperative Ring Oscillators
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Transmission Line Clock Driver
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Analysis and verification of interconnected rings as clock distribution networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Delay insertion method in clock skew scheduling
Proceedings of the 2005 international symposium on Physical design
A multi-level transmission line network approach for multi-giga hertz clock distribution
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A PLL Design based on a Standing Wave Resonant Oscillator
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Implementing digital logic with sinusoidal supplies
Proceedings of the Conference on Design, Automation and Test in Europe
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
A methodology for local resonant clock synthesis using LC-assisted local clock buffers
Proceedings of the International Conference on Computer-Aided Design
Library-aware resonant clock synthesis (LARCS)
Proceedings of the 49th Annual Design Automation Conference
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled, standing-wave oscillators and differential, low-swing clock buffers is presented. The measured results for a prototyped standing-wave clock grid operating at 10GHz and fabricated in a 0.18μm 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with sub-picosecond precision.