A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
Design methodology for global resonant H-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Resonant clocking is a form of adiabatic clocking that retains much of the energy present in clock switching and recycles it into the following clock cycle. In this paper we present the first automated methodology using LC-assisted local clock buffers (LCLCB) for generating local resonant clocks. This uses a single-buffer single-inductor sector topology applied to non-uniform trees as found in most ASIC designs. We show that this form of adiabatic clocking can achieve power savings as much as 75% over traditional buffered clock networks.