Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Design of Resonant Global Clock Distributions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Sensitivity evaluation of global resonant H-tree clock distribution networks
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Electrical and optical clock distribution networks for gigascale microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Efficient delay and crosstalk modeling of RLC interconnects using delay algebraic equations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quasi-resonant interconnects: a low power, low latency design methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of resonant clock distribution networks for 3-D integrated circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A methodology for local resonant clock synthesis using LC-assisted local clock buffers
Proceedings of the International Conference on Computer-Aided Design
Library-aware resonant clock synthesis (LARCS)
Proceedings of the 49th Annual Design Automation Conference
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
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Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described, supporting the design of low power, skew, and jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is presented that demonstrates the design of a two-level resonant H-tree network, distributing a 5-GHz clock signal in a 0.18-µm CMOS technology. This example exhibits an 84% decrease in power dissipation as compared to a standard H-tree clock distribution network. The design methodology enables tradeoffs among design variables to be examined, such as the operating frequency, the size of the on-chip inductors and capacitors, the output resistance of the driving buffer, and the interconnect width. A sensitivity analysis of resonant H-tree clock distribution networks is also provided. The effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing and power consumption is described.