Sensitivity evaluation of global resonant H-tree clock distribution networks
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design methodology for global resonant H-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 conference on Information Science, Technology and Applications
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enabling resonant clock distribution with scaled on-chip magnetic inductors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Quasi-resonant interconnects: a low power, low latency design methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
Design of resonant clock distribution networks for 3-D integrated circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a new approach to global clock distribution inwhich traditional tree-driven grids are augmented with on-chipinductors to resonate the clock capacitance at the fundamentalfrequency of the clock node. Rather than being dissipated as heat,the energy of the fundamental resonates between electric andmagnetic forms. The clock drivers must only provide the energynecessary to overcome losses. As a result, power reduction of over80% is possible depending on the Q of the resonant system. Clocklatency is also improved because the effective capacitance of thegrid is lower, and fewer buffer stages are necessary to drivethegrid. Skew and jitter reductions come about because of this reducedbuffer latency.