A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design methodology for global resonant H-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Clock grids are often used in high-performance ASIC designs because of their low skew and robustness to variations. Resonant clock grids have the potential to reduce the power consumption of these high-performance clocks without sacrificing the skew and robustness of a clock grid. We present the first methodology to synthesize high-performance distributed resonant LC tank clock grids that utilize a pre-characterized inductor library. The use of a library reduces designer effort and total inductor area when compared with previous resonant clock grids while still attaining 59% power reduction and competitive skew when compared to traditional buffered clock grids.