Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Communications of the ACM
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Introduction to VLSI Systems
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
Clocking strategies for networks-on-chip
Networks on chip
Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A multi-level transmission line network approach for multi-giga hertz clock distribution
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Sensitivity evaluation of global resonant H-tree clock distribution networks
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design methodology for global resonant H-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Quasi-resonant interconnects: a low power, low latency design methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
Design of resonant clock distribution networks for 3-D integrated circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A methodology for local resonant clock synthesis using LC-assisted local clock buffers
Proceedings of the International Conference on Computer-Aided Design
Synchronization scheme for brick-based rotary oscillator arrays
Proceedings of the great lakes symposium on VLSI
Library-aware resonant clock synthesis (LARCS)
Proceedings of the 49th Annual Design Automation Conference
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Proceedings of the Conference on Design, Automation and Test in Europe
ZeROA: zero clock skew rotary oscillatory array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The design of a synchronous system having a global clock must account for propagation-delay-induced phase shifts experienced by the clock signal (clock skew) in its distribution network. As clock speeds and system diameters increase, this requirement becomes increasingly constraining on system designs. The paper describes a method that exploits properties of standing waves to reduce substantially clock skews due to unequal path lengths, for distribution network diameters up to several meters. The basic principles are developed for a loaded transmission line, and then applied to an arbitrary branching tree of such lines to implement a clock distribution network. The extension of this method to two- and three-dimensional distribution media is also presented, suggesting the feasibility of implementing printed circuit board clock planes exhibiting negligible phase shift over their extents.