Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories

  • Authors:
  • Henry Fuchs;John Poulton;John Eyles;Trey Greer;Jack Goldfeather;David Ellsworth;Steve Molnar;Greg Turk;Brice Tebbs;Laura Israel

  • Affiliations:
  • Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Mathematics, Carleton College, Northfield, MN.;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC;Department of Computer Science, University of North Carolina, Chapel Hill, NC

  • Venue:
  • SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
  • Year:
  • 1989

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Abstract

This paper introduces the architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles/second) and for supporting algorithm and application research in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form-factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280 × 1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128 × 128-pixel array of processors-with-memory with parallel quadratic expression evaluation for every pixel. Implemented on 1.6 micron CMOS chips designed to run at 40MHz, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reasigned to any part of the screen or to non-screen-oriented computation. As of April 1989, both hardware and software are still under construction, with initial system operation scheduled for fall 1989.