On the design of a real-time volume rendering engine

Authors:
J. Smit;N. J. Wessels;A. van der Horst;M. J. Bentum
Affiliations:
-;-;-;-
Venue:
EGGH'92 Proceedings of the Seventh Eurographics conference on Graphics Hardware
Year:
1992

Citing 6
Cited 0

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Abstract

An architecture for a Real-Time Volume Rendering Engine is given capable of computing 750×750×512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISe-processors. An plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. The interpolator is now back from production. It has been tested an complied with our specifications.