A Configurable Pixel Cache for Fast Image Generation
IEEE Computer Graphics and Applications
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SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
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Computer graphics: principles and practice (2nd ed.)
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SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
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SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
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EGGH'94 Proceedings of the Ninth Eurographics conference on Graphics Hardware
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Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.