A fast shaded-polygon renderer
SIGGRAPH '86 Proceedings of the 13th annual conference on Computer graphics and interactive techniques
A rectangular area filling display system architecture
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
Parallel processing image synthesis and anti-aliasing
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
Dynamic scan-converted images with a frame buffer display device
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
A parallel processor system for three-dimensional color graphics
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Super buffer: a systolic vlsi graphics engine for real time raster image generation (graphics)
Super buffer: a systolic vlsi graphics engine for real time raster image generation (graphics)
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Real-time rendering of trimmed surfaces
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
A characterization of ten rasterization techniques
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
The rendering architecture of the DN10000VS
SIGGRAPH '90 Proceedings of the 17th annual conference on Computer graphics and interactive techniques
Real-time display of quadric on the I.M.O.G.E.N.E. machine
SMA '91 Proceedings of the first ACM symposium on Solid modeling foundations and CAD/CAM applications
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories
IEEE Computer Graphics and Applications
Pixel merging for object-parallel rendering: a distributed snooping algorithm
PRS '93 Proceedings of the 1993 symposium on Parallel rendering
FBRAM: a new form of memory optimized for 3D graphics
SIGGRAPH '94 Proceedings of the 21st annual conference on Computer graphics and interactive techniques
Heresy: a virtual image-space 3D rasterization architecture
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
PS: polygon streams a distributed architecture for incremental computation applied to graphics
EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
Two-level pipelining of systolic array graphics engines
EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
I.M.O.G.E.N.E.: a solution to the real time animation problem
EGGH'90 Proceedings of the Fifth Eurographics conference on Advances in Computer Graphics Hardware: rendering, ray tracing and visualization systems
An architecture for interactive raster graphics
EGGH'92 Proceedings of the Seventh Eurographics conference on Graphics Hardware
An efficient massively parallel rasterization scheme for a high performance graphics system
EGGH'92 Proceedings of the Seventh Eurographics conference on Graphics Hardware
Depth complexity in object-parallel graphics architectures
EGGH'92 Proceedings of the Seventh Eurographics conference on Graphics Hardware
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The desire for higher performance and higher resolution continuously increases the pixel update rates needed in high performance graphics systems. The increasing density of memory chips on the other hand reduces the pixel update rate that can be provided by the frame buffer. We present the design of a VLSI chip and a graphics system that can sustain sub-nanosecond pixel rendering rates for three-dimensional polygons and can be used to render about a million Z-Buffered and Gourard shaded polygons per second. The chip has been designed at the IBM Research Division's Thomas J. Watson Research Center.