VLSI array processors
A display controller for an object-level frame store system
Advances in computer graphics hardware III
Subanosecond pixel rendering with million transistor chips
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Display Architecture for VLSI-based Graphics Workstations
Advances in Computer Graphics Hardware I (Eurographics'86 Workshop)
PROOF: An Architecture for Rendering in Object Space
Advances in Computer Graphics Hardware III (Eurographics'88 Workshop)
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In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic army graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic army graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graphtheoretic approach. Furthermore, we characttTize the architectures which can be improved by pipelined functional units.