A Configurable Pixel Cache for Fast Image Generation
IEEE Computer Graphics and Applications
A characterization of ten rasterization techniques
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Computer graphics: principles and practice (2nd ed.)
Computer graphics: principles and practice (2nd ed.)
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Graphics rendering architecture for a high performance desktop workstation
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
Leo: a system for cost effective 3D shaded graphics
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
ACM Transactions on Graphics (TOG)
The triangle processor and normal vector shader: a VLSI system for high performance graphics
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Subanosecond pixel rendering with million transistor chips
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
High-performance polygon rendering
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A subdivision algorithm for computer display of curved surfaces.
A subdivision algorithm for computer display of curved surfaces.
HoloSketch: a virtual reality sketching/animation tool
ACM Transactions on Computer-Human Interaction (TOCHI) - Special issue on virtual reality software and technology
Heresy: a virtual image-space 3D rasterization architecture
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Accommodating memory latency in a low-cost rasterizer
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
The design and analysis of a cache architecture for texture mapping
Proceedings of the 24th annual international symposium on Computer architecture
Multi-level texture caching for 3D graphics hardware
Proceedings of the 25th annual international symposium on Computer architecture
Neon: a single-chip 3D workstation graphics accelerator
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Optimal depth buffer for low-cost graphics hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Tiled polygon traversal using half-plane edge functions
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Polygon rendering on a stream architecture
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
The SAGE graphics architecture
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Texram: A Smart Memory for Texturing
IEEE Computer Graphics and Applications
IEEE Micro
IEEE Micro
A consistency-free memory architecture for sort-last parallel rendering processors
Journal of Systems Architecture: the EUROMICRO Journal
A processor architecture with effective memory system for sort-last parallel rendering
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Hardware for superior texture performance
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
The setup for triangle rasterization
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. The first is to convert the read-modify-write Z-buffer compare and RGB&agr; blend into a single write only operation. The second is to support two levels of rectangularly shaped pixel caches internal to the memory chip. The result is a 10 megabit part that, for 3D graphics, performs read-modify-write cycles ten times faster than conventional 60 ns VRAMs. A four-way interleaved 100MHz FBRAM frame buffer can Z-buffer up to 400 million pixels per second. Working FBRAM prototypes have been fabricated.