Wisconsin Architectural Research Tool Set
ACM SIGARCH Computer Architecture News
A Sorting Classification of Parallel Rendering
IEEE Computer Graphics and Applications
FBRAM: a new form of memory optimized for 3D graphics
SIGGRAPH '94 Proceedings of the 21st annual conference on Computer graphics and interactive techniques
VC-1: a scalable graphics computer with virtual local frame buffers
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
R-buffer: a pointerless A-buffer hardware architecture
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
The A -buffer, an antialiased hidden surface method
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Delay streams for graphics hardware
ACM SIGGRAPH 2003 Papers
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
IEEE Transactions on Computers
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In this paper, a consistency-free memory architecture for sort-last parallel rendering processors with a single frame buffer is proposed to resolve the consistency problem which may occur when more than one rasterizer try to access the data at the same address. Also, the proposed architecture reduces the latency due to pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. For these goals, a consistency-free pixel cache architecture and three effective memory systems with consistency-test units are presented. The experimental results show that the proposed architecture can achieve almost linear speedup up to four rasterizers with a single frame buffer.