Computer graphics: principles and practice (2nd ed.)
Computer graphics: principles and practice (2nd ed.)
Wisconsin Architectural Research Tool Set
ACM SIGARCH Computer Architecture News
Hierarchical Z-buffer visibility
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
InfiniteReality: a real-time graphics system
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
The design and analysis of a cache architecture for texture mapping
Proceedings of the 24th annual international symposium on Computer architecture
Unsolved problems and opportunities for high-quality, high-performance 3D graphics on a PC platform
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Prefetching in a texture cache architecture
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
IEEE Computer Graphics and Applications
The Truga001: A Scalable Rendering Processor
IEEE Computer Graphics and Applications
The Wild World of 3D Graphics Chips
Computer
The setup for triangle rasterization
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
An Effective Visibility Culling Method Based on Cache Block
IEEE Transactions on Computers
A consistency-free memory architecture for sort-last parallel rendering processors
Journal of Systems Architecture: the EUROMICRO Journal
Technical Section: Area-efficient pixel rasterization and texture coordinate interpolation
Computers and Graphics
A processor architecture with effective memory system for sort-last parallel rendering
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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As a 3D scene becomes increasingly complex and the screen resolution increases, the design of an effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture that performs the depth test twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste due to fetching unnecessary obscured texture data by performing the depth test before texture mapping. It also reduces the miss penalties of the pixel cache by using a prefetch scheme驴that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. We have built a trace-driven simulator for the proposed architecture. To validate the proposed architecture, the results of various simulations are provided. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption while producing high-performance gains.