PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Wisconsin Architectural Research Tool Set
ACM SIGARCH Computer Architecture News
A Sorting Classification of Parallel Rendering
IEEE Computer Graphics and Applications
FBRAM: a new form of memory optimized for 3D graphics
SIGGRAPH '94 Proceedings of the 21st annual conference on Computer graphics and interactive techniques
VC-1: a scalable graphics computer with virtual local frame buffers
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
InfiniteReality: a real-time graphics system
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
WireGL: a scalable graphics system for clusters
Proceedings of the 28th annual conference on Computer graphics and interactive techniques
R-buffer: a pointerless A-buffer hardware architecture
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
The Truga001: A Scalable Rendering Processor
IEEE Computer Graphics and Applications
The A -buffer, an antialiased hidden surface method
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Delay streams for graphics hardware
ACM SIGGRAPH 2003 Papers
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
IEEE Transactions on Computers
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Current rendering processors are aiming to process triangles as fast as possible and they have the tendency of equipping with multiple rasterizers to be capable of handling a number of triangles in parallel for increasing polygon rendering performance. However, those parallel architectures may have the consistency problem when more than one rasterizer try to access the data at the same address. This paper proposes a consistency-free memory architecture for sort-last parallel rendering processors, in which a consistency-free pixel cache architecture is devised and effectively associated with three different memory systems consisting of a single frame buffer, a memory interface unit, and consistency-test units. Furthermore, the proposed architecture can reduce the latency caused by pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. The experimental results show that the proposed architecture can achieve almost linear speedup upto four rasterizers with a single frame buffer.