A Configurable Pixel Cache for Fast Image Generation
IEEE Computer Graphics and Applications
Modeling the effect of the atmosphere on light
ACM Transactions on Graphics (TOG)
Faster phong shading via angular interpolation
Computer Graphics Forum
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
The triangle processor and normal vector shader: a VLSI system for high performance graphics
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Simulation of wrinkled surfaces
SIGGRAPH '78 Proceedings of the 5th annual conference on Computer graphics and interactive techniques
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
An Architecture based on the Memory Mapped Node Addressing in Reconfigurable Interconnection Network
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
ICMCS '96 Proceedings of the 1996 International Conference on Multimedia Computing and Systems
Creating Realistic Scenes in Future Multimedia Systems
IEEE MultiMedia
An effective hardware architecture for bump mapping using angular operation
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
IEEE Transactions on Computers
Power-Aware 3D Computer Graphics Rendering
Journal of VLSI Signal Processing Systems
A consistency-free memory architecture for sort-last parallel rendering processors
Journal of Systems Architecture: the EUROMICRO Journal
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The Truga001 is a single-chip rendering processor intended for virtual reality and multimedia systems. It has three main features: (1) multiple embedded functions with a MIMD structure that includes Phong shading, bump and texture mapping, reflection and refraction mapping, gaseous object rendering, shadow casting and hidden surface removal, (2) the combination of HDTV video camera images with CG images, and (3) scalability. It embeds twelve graphic processors and seven special modules in a single chip. The reconfigurable FIFO-memory pixel cache and three-dimensional frame buffer structure are used for high-speed transmission between the chip and frame buffers. A chip can simultaneously draw four million (10-pixel, arbitrarily sloped) vectors/s and render 1.2 million (1-pixel 3D triangles) polygons/s while applying Phong shading, bump and texture mapping, and hidden surface removal in a frame buffer system, implemented as a single-port DRAM. A system can also be scaled up with a parallel network of multiple Truga001s graphics processors. The chip can be fabricated in CMOS with 940.000 gates.