The triangle processor and normal vector shader: a VLSI system for high performance graphics

  • Authors:
  • Michael Deering;Stephanie Winner;Bic Schediwy;Chris Duffy;Neil Hunt

  • Affiliations:
  • Sun Microsystems Inc., 2550 Garcia Avenue, Mountain View, CA and Schlumberger Palo Alto Research, 3340 Hillview Avenue, Palo Alto, CA;Apple Computer Inc., 20525 Mariani Avenue, Cupertino, CA and Schlumberger Palo Alto Research, 3340 Hillview Avenue, Palo Alto, CA;Hewlett Packard Labs (3-U), 1501 Page Mill Road, Palo Alto, CA and Schlumberger Palo Alto Research, 3340 Hillview Avenue, Palo Alto, CA;Schlumberger Palo Alto Research, 3340 Hillview Avenue, Palo Alto, CA;Schlumberger Palo Alto Research, 3340 Hillview Avenue, Palo Alto, CA

  • Venue:
  • SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
  • Year:
  • 1988

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Abstract

Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but to date only at very high cost. We describe a new more affordable VLSI solution. A pipeline of triangle processors rasterizes the geometry, then a further pipeline of shading processors applies Phong shading with multiple light sources. The triangle processor pipeline performs 100 billion additions per second, and the shading pipeline performs two billion multiplies per second. This allows 3D graphics systems to be built capable of displaying more than one million triangles per second. We show the results of an anti-aliasing technique, and discuss extensions to texture mapping, shadows, and environment maps.