SIGGRAPH '86 Proceedings of the 13th annual conference on Computer graphics and interactive techniques
An exact incremental hidden surface removal algorithm
Advances in computer graphics hardware II
A vector-like architecture for raster graphics
Advances in computer graphics hardware II
Faster phong shading via angular interpolation
Computer Graphics Forum
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Parallel object-space hidden surface removal
SIGGRAPH '90 Proceedings of the 17th annual conference on Computer graphics and interactive techniques
The rendering architecture of the DN10000VS
SIGGRAPH '90 Proceedings of the 17th annual conference on Computer graphics and interactive techniques
A display controller for an object-level frame store system
Advances in computer graphics hardware III
The triangle processor and normal vector shader: a VLSI system for high performance graphics
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Subanosecond pixel rendering with million transistor chips
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Display Architecture for VLSI-based Graphics Workstations
Advances in Computer Graphics Hardware I (Eurographics'86 Workshop)
XInPosse: Structural Simulation for Graphics Hardware
Rendering, Visualization and Rasterization Hardware (Eurographics'91 Workshop)
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A radical reappraisal of the 3-D Interactive raster graphics pipeline has resulted In an experimental architecture for a workstation which is currently being evaluated at the CWI. The principal features of this architecture are that It: - concentrates exclusively on real-time interactive 3-D graphics (initially for CAD). - uses object space rather than Image space methods where possible. - avoids using a frame buffer. - only uses custom VLSI where commercial products are unlikely to suffice In the near term. Four years into the project the system design is complete and the major components have been acquired and the custom VLSI chips hove been packaged and tested. The current experience with the system is based on detailed simulations which gave a fairiy clear Idea on its strengths and limitations. A complete, but reduced resolution, experimental prototype system is now being assembled.