SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Parallel computers for graphics applications
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The Reyes image rendering architecture
SIGGRAPH '87 Proceedings of the 14th annual conference on Computer graphics and interactive techniques
The Flex architecture, a high speed graphics processor
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
The pixel machine: a parallel image computer
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Three-dimensional medical imaging: algorithms and computer systems
ACM Computing Surveys (CSUR)
Fast data parallel polygon rendering
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Talisman: commodity realtime 3D graphics for the PC
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
Design for a real-time high-quality volume rendering workstation
VVS '89 Proceedings of the 1989 Chapel Hill workshop on Volume visualization
Polygon rendering on a stream architecture
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
The triangle processor and normal vector shader: a VLSI system for high performance graphics
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A display system for the Stellar graphics supercomputer model GS1000
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A user-programmable vertex engine
Proceedings of the 28th annual conference on Computer graphics and interactive techniques
Using modern graphics architectures for general-purpose computing: a framework and analysis
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware
ACM Transactions on Architecture and Code Optimization (TACO)
Throughput-Effective On-Chip Networks for Manycore Accelerators
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Hardware transactional memory for GPU architectures
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
SIMD re-convergence at thread frontiers
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
International Journal of High Performance Computing Applications
On the correctness of the SIMT execution model of GPUs
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
Patchwork: A fast interpreter for a restricted dataflow language
Journal of Systems and Software
A VLSI architecture for image composition
EGGH'88 Proceedings of the Third Eurographics conference on Advances in Computer Graphics Hardware
A real-time raster scan display for 3-D graphics
EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
Efficient scheduling of recursive control flow on GPUs
Proceedings of the 27th international ACM conference on International conference on supercomputing
SIMD divergence optimization through intra-warp compaction
Proceedings of the 40th Annual International Symposium on Computer Architecture
Designing on-chip networks for throughput accelerators
ACM Transactions on Architecture and Code Optimization (TACO)
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Special purpose processing systems designed for specific applications can provide extremely high performance at moderate cost. One such processor is presented for executing graphics and image processing algorithms as the basis of a digital film printer. Pixels in the system contain four parallel components: RGB for full color and an alpha channel for retaining transparency information. The data path of the processor contains four arithmetic elements connected through a crossbar network to a tessellated scratchpad memory. The single instruction, multiple data stream (SIMD) processor executes instructions on four pixel components in parallel. The instruction control unit (ICU) maintains an activity stack for tracking block-structured code, using data-dependent activity flags for conditional disabling subsets of the ALUs. Nested loops and if-then-else constructs can be programmed directly, with the ICU disabling and reenabling ALUs on the basis of their individual status bits.