A fast shaded-polygon renderer
SIGGRAPH '86 Proceedings of the 13th annual conference on Computer graphics and interactive techniques
Compositing 3-D rendered images
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
A parallel scan conversion algorithm with anti-aliasing for a general-purpose ultracomputer
SIGGRAPH '83 Proceedings of the 10th annual conference on Computer graphics and interactive techniques
The Geometry Engine: A VLSI Geometry System for Graphics
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
Parallel processing image synthesis and anti-aliasing
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
A hidden-surface algorithm with anti-aliasing
SIGGRAPH '78 Proceedings of the 5th annual conference on Computer graphics and interactive techniques
Chap - a SIMD graphics processor
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
The A -buffer, an antialiased hidden surface method
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
A Comparison of Antialiasing Techniques
IEEE Computer Graphics and Applications
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This paper describes a new parallel architecture for performing high-speed raster graphics. A central host broadcasts graphical objects to a number of identical graphics processors Each graphics processor produces a raster depicting Its graphical object on a transparent black background. and passes the raster to a leaf of a tree of VLSI processors called Compositors. Each Compositor combines a pair of rasters, performing anti-aliased hidden surface removal, and passes the composed raster to the next level of the tree, Appearing at the root of the tree is the final raster containing all objects at the correct depth with hidden surfaces removed. This paper gives an outline of the algorithm by Duff that the Compositor Will implement The algorithm proves to be too complex for our implementation technology, so a modification of Duff's algorithm is introduced. The high-level design of the dataflow part of the VLSI chip which implements this modified algorithm is then presented, followed by performance simulations and conclusions.