Fundamentals of interactive computer graphics
Fundamentals of interactive computer graphics
A parallel processor architecture for graphics arithmetic operations
SIGGRAPH '87 Proceedings of the 14th annual conference on Computer graphics and interactive techniques
Advances in computer graphics hardware II
A VLSI architecture for image composition
Advances in computer graphics hardware III
Compositing 3-D rendered images
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
The triangle processor and normal vector shader: a VLSI system for high performance graphics
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
High-performance polygon rendering
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A display system for the Stellar graphics supercomputer model GS1000
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
SIGGRAPH '83 Proceedings of the 10th annual conference on Computer graphics and interactive techniques
The A -buffer, an antialiased hidden surface method
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Summed-area tables for texture mapping
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
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Described is a hardware architecture for combining the outputs of a number of z-buffer rendering engines to achieve higher performance than is possible with a single renderer. It allows a combination of renderers to achieve the same price/ performance ratio as the individual renderers that compose it, and can be extended to create systems with arbitrarily high performance. The described architecture is based on a fusion of scan-line rendering and the conventional z-buffer algorithm. The frame buffers of several z-buffer engines are modified to scan out z-values as well as color values. Multiplexing devices combine the z/color streams from each pair of frame-buffers. These z/color streams are then combined by further multiplexers, creating a binary tree that funnels the z/color information from the many conventional frame buffers into a single z/color stream. The color stream is then used to dnve a standard display device. The proposed architecture allows rendering rates of millions and even tens of millions of polygons per second. The basic architecture can be extended with additional hardware to perform antialiasing and texture-mapping.