Wisconsin Architectural Research Tool Set
ACM SIGARCH Computer Architecture News
Hierarchical Z-buffer visibility
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
Extending graphics hardware for occlusion queries in OpenGL
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Prefetching in a texture cache architecture
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Effective occlusion culling for the interactive display of arbitrary models
Effective occlusion culling for the interactive display of arbitrary models
IEEE Computer Graphics and Applications
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
IEEE Transactions on Computers
| Hi-index | 14.98 |
As the complexity of 3D scenes is on the increase, the search for an effective visibility culling method has become one of the most important issues to be addressed in the design of 3D rendering processors. In this paper, we propose a new rasterization pipeline with visibility culling; the proposed architecture performs the visibility culling at an early stage of the rasterization pipeline (especially at the traversal stage) by retrieving data in a pixel cache without any significant hardware logics such as the hierarchical z{\hbox{-}}{\rm buffer}. If the data to be retrieved does not exist in the pixel cache, the proposed architecture performs a prefetch operation in order to reduce the miss penalty of the pixel cache. That is, the cache miss penalty can be reduced as the transfer of a missed cache block from the frame memory into the pixel cache can be handled simultaneously with the rasterization pipeline executions. Simulation results show that the proposed architecture can achieve a performance gain of about 32 percent compared with the conventional pretexturing architecture and about 7 percent compared to the hierarchical z{\hbox{-}}{\rm buffer} visibility scheme.