Algorithms for division free perspective correct rendering
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Tiled polygon traversal using half-plane edge functions
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A parallel algorithm for polygon rasterization
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Incremental and hierarchical Hilbert order edge equation polygon rasterizatione
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
3d Computer Graphics
MIP-Map Level Selection for Texture Mapping
IEEE Transactions on Visualization and Computer Graphics
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Graphics for the masses: a hardware rasterization architecture for mobile phones
ACM SIGGRAPH 2003 Papers
Quadratic Interpolation in Hardware Phong Shading and Texture Mapping
SCCG '01 Proceedings of the 17th Spring conference on Computer graphics
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
IEEE Transactions on Computers
A Cost-Effective Pipelined Divider with a Small Lookup Table
IEEE Transactions on Computers
ACM Transactions on Graphics (TOG)
Half-tone perspective drawings by computer
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
Study on rasterization algorithm for graphics acceleration system
ICONIP'12 Proceedings of the 19th international conference on Neural Information Processing - Volume Part V
Technical Section: Energy-aware hybrid precision selection framework for mobile GPUs
Computers and Graphics
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In this paper, new pixel rasterization and texture coordinate interpolation algorithms are presented to reduce silicon area. The proposed pixel rasterization based on the characteristics of edge function saves silicon area in terms of gate count by 38.9% and 35.3% compared to the previous centerline and scanline algorithms, respectively. The proposed texture coordinate interpolation combines the benefits of division and midpoint iteration in order to reduce silicon area without performance loss in computing the fraction part of texture coordinates, which is required for texture filtering. The proposed texture coordinate interpolation architecture uses less silicon gates than the architecture using dividers, and the gate count reduction ratios are 25.2% and 37.0% for 16- and 32-bit texture coordinates, respectively. The hardware feasibility of the proposed architecture is proved by implementation into a three-dimensional (3D) graphics SoC.