Tiled polygon traversal using half-plane edge functions
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A parallel algorithm for polygon rasterization
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Incremental and hierarchical Hilbert order edge equation polygon rasterizatione
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A High-Performance Area-Efficient Multifunction Interpolator
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
ACM Transactions on Graphics (TOG)
Fast 3D triangle-box overlap testing
SIGGRAPH '05 ACM SIGGRAPH 2005 Courses
Technical Section: Area-efficient pixel rasterization and texture coordinate interpolation
Computers and Graphics
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The 3D devices have been widely applied in people's life, for example, smart phone, internet games, high-definition video, geography navigation, etc. The large scale graphics rendering depends on the computing power of the hardware greatly, the calculation of model rasterization operations need amounts of data. It has become the bottleneck of system performance. This paper proposed the method which can accelerate graphics rasterization procedure, based on the idea of tile to meet the needs of graphical applications on embedded platform. The rules and procedures of algorithm are introduced. By using of the XUP-LX110T, the experiments are carried out. It is verified that the method should been compensated the features for the lack of resources and poor computing power of embedded platforms. It can apply smaller chip area to achieve graphics acceleration with fewer resources.