The design and analysis of a cache architecture for texture mapping
Proceedings of the 24th annual international symposium on Computer architecture
A parallel algorithm for polygon rasterization
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A Retargetable C Compiler: Design and Implementation
A Retargetable C Compiler: Design and Implementation
Color Recovery: True-Color 8-Bit Interactive Graphics
IEEE Computer Graphics and Applications
Hybrid volume and polygon rendering with cube hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A superscalar 3D graphics engine
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Dynamic 3D graphics workload characterization and the architectural implications
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Graphics for the masses: a hardware rasterization architecture for mobile phones
ACM SIGGRAPH 2003 Papers
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
IEEE Transactions on Computers
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High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL 3D rendering, and X11 and Windows/NT 2D rendering. Since our pin budget limited memory bandwidth, we designed Neon from the memory system upward to reduce bandwidth requirements. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital's Alpha CPUs. Neon-based boards compete well against other workstation accelerators, but cost much less due to a small part count and use of commodity SDRAMs.