A VLSI architecture for updating raster-scan displays
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
An Efficient Buffer Memory System for Subarray Access
IEEE Transactions on Parallel and Distributed Systems
Subanosecond pixel rendering with million transistor chips
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Hierarchical Data Structures and Algorithms for Computer Graphics
IEEE Computer Graphics and Applications
A Multiaccess Frame Buffer Architecture
IEEE Transactions on Computers
A parallel scan conversion algorithm with anti-aliasing for a general-purpose ultracomputer
SIGGRAPH '83 Proceedings of the 10th annual conference on Computer graphics and interactive techniques
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A display system architecture which has rectangular area filling as its primitive operation is presented. It is shown that lines can be drawn significantly faster with this architecture than with a pixel display system. The rendition of filled boxes is also faster showing an O(n2) speed improvement. Furthermore filled polygons can be rendered with an O(n) speed improvement. The design and implementation of this rectangular area filling architecture are discussed and refined. A custom VLSI integrated circuit is currently being designed to implement this rectangular area filling architecture and at the same time reduce the display memory system video refresh bandwidth requirements.