An Efficient Memory System for Image Processing
IEEE Transactions on Computers
Frame-buffer display architectures
Annual review of computer science vol. 1, 1986
An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid
IEEE Transactions on Parallel and Distributed Systems
ACM Transactions on Graphics (TOG)
A Multiaccess Frame Buffer Architecture
IEEE Transactions on Computers
A rectangular area filling display system architecture
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
A 2D Addressing Mode for Multimedia Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A 2D addressing mode for multimedia applications
Embedded processor design challenges
Multiaccess Memory System for Attached SIMD Computer
IEEE Transactions on Computers
An optimized linear skewing interleave scheme for on-chip multi-access memory systems
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Memory organization with multi-pattern parallel accesses
Proceedings of the conference on Design, automation and test in Europe
High-bandwidth Address Generation Unit
Journal of Signal Processing Systems
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Many current graphical display systems utilize a buffer memory system to contain a two-dimensional image array to be modified and displayed. In order to speed up the update of the buffer memory system, it is required that the buffer memory system accesses many image points within an image subarray in parallel. This paper proposes an efficient buffer memory system for a fast and high-resolution graphical display system. The memory system provides parallel accesses to $pq$ image points within a ${\rm{block(p \times q)}}$, a ${\rm{horizontal(1 \times pq)}}$, a ${\rm{vertical(pq \times 1)}}$, a forward-diagonal, or a backward-diagonal subarray in a two-dimensional image array, ${\rm{M \times N}}$, where the design parameters $p$ and $q$ are all powers of two. In the address calculation and routing circuit of the proposed buffer memory system, the address differences of the five subarrays are prearranged according to the index numbers of memory modules and stored in two Static Random Access Memories (SRAMs), so that the address differences are simply added to the base address to obtain the addresses according to the index numbers of memory modules. In addition, for the fast address calculation, one single multiplication operation in the base address calculation is replaced by a SRAM access, so that the multiplication operation can be performed during the SRAM access for the address differences for the case when N is not a power of two. The address calculation and routing circuit proposed in this paper is improved in the hardware cost, the complexity of control, and the speed over the previous circuits.