Conflict-Free Vector Access Using a Dynamic Storage Scheme
IEEE Transactions on Computers
Proceedings of the 27th annual international symposium on Computer architecture
An Efficient Buffer Memory System for Subarray Access
IEEE Transactions on Parallel and Distributed Systems
Conflict-Free Access for Streams in Multimodule Memories
IEEE Transactions on Computers
Conflict-Free Accesses to Strided Vectors on a Banked Cache
IEEE Transactions on Computers
Memory access pattern analysis and stream cache design for multimedia applications
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
Parallel Memory Architecture for Arbitrary Stride Accesses
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Multimedia rectangularly addressable memory
IEEE Transactions on Multimedia
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We propose an interleaved memory organization supporting multi-pattern parallel accesses in two-dimensional (2D) addressing space. Our proposal targets computing systems with high memory bandwidth demands such as vector processors, multimedia accelerators, etc. We substantially extend prior research on interleaved memory organizations introducing 2D-strided accesses along with additional parameters, which define a large variety of 2D data patterns. The proposed scheme guarantees minimum memory latency and efficient bandwidth utilization for arbitrary configuration parameters of the data pattern. We provide mathematical descriptions and proofs of correctness for the proposed addressing schemes. The design complexity and the critical paths are evaluated using technology independent resource counts and confirm the scalability of the proposal. Hardware synthesis results for 90nm CMOS technology suggest that throughputs in the range between 44 and 1182 Gbit/s can be obtained at the cost of 26-212 Kgates for configurations of 2x2 32-bit up to 8x8 64-bit memory modules.