A Simulation Study of the CRAY X-MP Memory System
IEEE Transactions on Computers
An Efficient Memory System for Image Processing
IEEE Transactions on Computers
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
On Linear Skewing Schemes and d-Ordered Vectors
IEEE Transactions on Computers
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Linear-time Matrix Transpose Algorithms Using Vector Register File With Diagonal Registers
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
A 2D Addressing Mode for Multimedia Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Access ordering and memory-conscious cache utilization
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Memory access reordering in vector processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Configurable implementation of parallel memory based real-time video downscaler
Microprocessors & Microsystems
PSIM: Periodically Shifted Interleaved Memory System
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A One's Complement Cache Memory
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Bounded-Collision Memory-Mapping Schemes for Data Structures with Applications to Parallel Memories
IEEE Transactions on Parallel and Distributed Systems
Memory Systems for Image Processing
IEEE Transactions on Computers
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
IEEE Transactions on Computers
The Piecewise Data Flow Architecture: Architectural Concepts
IEEE Transactions on Computers
The Burroughs Scientific Processor (BSP)
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
Theoretical Limitations on the Efficient Use of Parallel Memories
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
Time and Parallel Processor Bounds for Linear Recurrence Systems
IEEE Transactions on Computers
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations
IEEE Transactions on Computers
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Sams: single-affiliation multiple-stride parallel memory scheme
Proceedings of the 2008 workshop on Memory access on future processors: a solved problem?
Memory organization with multi-pattern parallel accesses
Proceedings of the conference on Design, automation and test in Europe
Supercomputers for ordinary users
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit
Journal of Signal Processing Systems
Parallel Memory Architecture for Application-Specific Instruction-Set Processors
Journal of Signal Processing Systems
High-bandwidth Address Generation Unit
Journal of Signal Processing Systems
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
Microprocessors & Microsystems
Paper: Nearest neighbor classification on two types of SIMD machines
Parallel Computing
Parallel memory architecture for TTA processor
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
SAMS multi-layout memory: providing multiple views of data to boost SIMD performance
Proceedings of the 24th ACM International Conference on Supercomputing
The multidimensional access memory in STARAN
IEEE Transactions on Computers - Special issue on parallel processors and processing
A performance study of buffered pseudorandomly interleaved memories with multiple sections
Mathematical and Computer Modelling: An International Journal
The conveyor: an interconnection device for parallel volumetric transformations
EGGH'91 Proceedings of the Sixth Eurographics conference on Advances in Computer Graphics Hardware: rendering, visualization and rasterization hardware
| Hi-index | 15.03 |
As computer CPUs get faster, primary memories tend to be organized in parallel banks. The fastest machines now being developed can fetch of the order of 100 words in parallel. Unless memory and compiler designers are careful, serious memory conflicts and resulting performance degradation may result. Some of the important questions of design and use of such memories are discussed.