A fast division technique for constant divisors
Communications of the ACM
Theoretical limitations on the use of parallel memories.
Theoretical limitations on the use of parallel memories.
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
IEEE Transactions on Computers
The Burroughs Scientific Processor (BSP)
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
Implementation of Permutation Functions in Illiac IV-Type Computers
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Interconnections for Parallel Memories to Unscramble p-Ordered Vectors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
A Simulation Study of the CRAY X-MP Memory System
IEEE Transactions on Computers
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
A Characterization and Analysis of Parallel Processor Interconnection Networks
IEEE Transactions on Computers
Discrete Optimization Problem in Local Networks and Data Alignment
IEEE Transactions on Computers
Multiple Templates Access of Trees in Parallel Memory Systems
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Memory access reordering in vector processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Toward a Universal Mapping Algorithm for Accessing Trees in Parallel Memory Systems
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
PSIM: Periodically Shifted Interleaved Memory System
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
The Burroughs Scientific Processor (BSP)
IEEE Transactions on Computers
Conflict-free memory allocation for associative data files
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
High-bandwidth Address Generation Unit
Journal of Signal Processing Systems
Memory Allocations for Multiprocessor Systems That Incorporate Content-Addressable Memories
IEEE Transactions on Computers
A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness
CASCON First Decade High Impact Papers
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 15.01 |
In this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation.