A dynamic storage scheme for conflict-free vector access
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Perfect Latin squares and parallel array access
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
On randomly interleaved memories
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
The Chinese remainder theorem and the prime memory system
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
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Interleaved memory schemes have been used to increase the memory bandwidth. In this paper, we propose a new interleaved memory scheme called PSIM (Periodically Shifted Interleaved Memory), which allows high memory bandwidths at the sacrifice of very small memory space. It is a stride dependent scheme where the processor utilization is 100% for most strides using a power-of-two number of memory modules. We show, analytically and then by simulation, that the efficiency of PSIM is consistently higher than not only earlier stride dependent schemes but also stride independent schemes for both short and long vector accesses