On the effective bandwidth of interleaved memories in vector processor systems
IEEE Transactions on Computers
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Scrambled storage for parallel memory systems
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
An aperiodic storage scheme to reduce memory conflicts in vector processors
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Data Organization in Parallel Computers
Data Organization in Parallel Computers
Pseudo-randomly interleaved memory
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Using Lookahead to reduce memory bank contention for decoupled operand references
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Measurement of memory access contentions in multiple vector processor systems
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
A novel cache design for vector processing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Introducing a New Cache Design into Vector Computers
IEEE Transactions on Computers
Accounting for memory bank contention and delay in high-bandwidth multiprocessors
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
The design and performance of a conflict-avoiding cache
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Bounding on the gain of optimizing data layout in vector processors
ICS '98 Proceedings of the 12th international conference on Supercomputing
Randomized Cache Placement for Eliminating Conflicts
IEEE Transactions on Computers - Special issue on cache memory and related problems
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems
IEEE Transactions on Computers
Increasing the effective bandwidth of complex memory systems in multivector processors
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
IEEE Transactions on Computers
Reducing Interference Among Vector Accesses in Interleaved Memories
IEEE Transactions on Computers
Analytical Estimation of Vector Access Performance in Parallel Memory Architectures
IEEE Transactions on Computers
Memory access reordering in vector processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Multiaccess Memory System for Attached SIMD Computer
IEEE Transactions on Computers
Eliminating Conflict Misses Using Prime Number-Based Cache Indexing
IEEE Transactions on Computers
IEEE Transactions on Computers
PSIM: Periodically Shifted Interleaved Memory System
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Memory scheduling for modern microprocessors
ACM Transactions on Computer Systems (TOCS)
High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A comparative analysis of performance improvement schemes for cache memories
Computers and Electrical Engineering
Return data interleaving for multi-channel embedded CMPs systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Memory address interleaving, where an address k generated by a processor is mapped into the memory bank k (mod m), is a basic technique for increasing memory bandwidth. However, the access conflicts that can occur in interleaved memories sometimes reduce the bandwidth gain significantly, especially in vector processors. Recently, a few random interleaving schemes have been proposed to reduce memory contention. We define a class of such methods, called LINEAR, that uses linear transformations of addresses for randomization and includes those used in the RP3 and Cydra 5 computers. After identifying a basic deficiency of LINEAR, we define a new class of random interleaving methods called RANDOM-H and, through comparative analysis, show that RANDOM-H performs better than LINEAR. To illustrate RANDOM-H, we describe MASH, which is a random interleaving technique based on multiplicative hashing. Our simulation results indicate that MASH generally performs better than typical linear methods.