A fault-tolerant scheme for multistage interconnection networks
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Design and analysis of fault-tolerant multistage interconnection networks with low link complexity
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
The performance analysis of partitioned circuit switched multistage interconnection networks
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Performance analysis of circuit switching, baseline interconnection networks
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Connection principles for multipath, packet switching networks
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
VLSI Performance Comparison of Banyan and Crossbar Communications Networks
IEEE Transactions on Computers
On the Number of Permutations Performable by the Augmented Data Manipulator Network
IEEE Transactions on Computers
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
A Class of Redundant Path Multistage Interconnection Networks
IEEE Transactions on Computers
On the Bandwidth and Interference in Interleaved Memory Systems
IEEE Transactions on Computers
Equivalence Between Functionality and Topology of Log N-Stage Banyan Networks
IEEE Transactions on Computers
Hierarchical Classification of Permutation Classes in Multistage Interconnection Networks
IEEE Transactions on Computers
A new approach to fast control of r2× r2 3-stage benes networks of r×r crossbar switches
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
On Evil Twin Networks and the Value of Limited Randomized Routing
IEEE Transactions on Parallel and Distributed Systems
Assessing Reliability of Multistage Interconnection Networks
IEEE Transactions on Computers
An O(log2 N) Depth Asymptotically Nonblocking Self-Routing Permutation Network
IEEE Transactions on Computers
Partitioning Message Patterns for Bundled Omega Networks
IEEE Transactions on Parallel and Distributed Systems
Generic model and analysis of asymmetric spanke optical switch configuration
ICCC '02 Proceedings of the 15th international conference on Computer communication
A universal performance factor for multi-criteria evaluation of multistage interconnection networks
Future Generation Computer Systems - Systems performance analysis and evaluation
Evolutionary optimization of multistage interconnection networks performance
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
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We present analytic models for the blocking probability of both unique path and multiple path multistage interconnection networks under the assumption of either permutation or random memory request patterns. The blocking probability of an interconnection network under the assumption of permutation requests is a quantitative measure of the network's permutation capability. We compare the performance of networks with approximately equivalent hardware complexity. It is shown that variations of banyan networks can be designed with extremely low blocking probabilities under the assumption of permutation requests.