Experience Using Multiprocessor Systems—A Status Report
ACM Computing Surveys (CSUR)
Data-Driven and Demand-Driven Computer Architecture
ACM Computing Surveys (CSUR)
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Performance measurements on HEP - a pipelined MIMD computer
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Switching strategies in a class of packet switching networks
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Building blocks for data flow prototypes
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Packet switching in banyan networks
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Pipelining and dataflow techniques for designing supercomputers
Pipelining and dataflow techniques for designing supercomputers
Communication nets; stochastic message flow and delay
Communication nets; stochastic message flow and delay
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
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Packet switched Multistage Interconnection Networks (MINs) have been mostly proposed to use unique connection path between any source and destination. We propose to add a few extra stages in an MIN to create multiple paths between any source and destination. Connection principles of Multipath MINs (MMINs) for packet switching are presented in this paper. Performance of such network is analyzed for possible use in multiprocessor systems and dataflow computers. For an MMIN with n nodes, the number of required stages is confined in the range [log2n+1, 2log2n-1]. Each stage consists of n/2 buffered 2-by-2 switching cells. In practice, one or two extra stages is sufficient beyond log2n stages required in a unique-path MIN. The delays of MMINs are shown much shorter than that of using unique-path MINs for packet switching. The improvement lies in significantly reduced packet wait delays in buffers, especially under heavy traffic conditions. The tradeoffs between reduced network delays and increased hardware cost are studied. Optimal design criteria and procedures are provided for developing MMINs with a fixed network size and stages.