The connection machine
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Architectural support for the efficient generation of code for horizontal architectures
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A multiple processor data flow machine that supports generalized procedures
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
QAS*APL: A step towards program-free interactive problem solving
APL '79 Proceedings of the international conference on APL: part 1
Man-machine interface design for timesharing systems
ACM '76 Proceedings of the 1976 annual conference
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Software psychology: Human factors in computer and information systems (Winthrop computer systems series)
Survey on special purpose computer architectures for AI
ACM SIGART Bulletin
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Incorporating data flow ideas into von neumann processors for parallel execution
IEEE Transactions on Computers
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
BVE: a wafer-scale engine for differential equation computation
ICS '88 Proceedings of the 2nd international conference on Supercomputing
A compilation technique for software pipelining of loops with conditional jumps
ACM SIGMICRO Newsletter
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Distributed Instruction Set Computer Architecture
IEEE Transactions on Computers
SPIRE: streaming processing with instructions release element
ACM SIGARCH Computer Architecture News
Exploiting heterogeneous parallelism on a multithreaded multiprocessor
ICS '92 Proceedings of the 6th international conference on Supercomputing
Empirical study of latency hiding on a fine-grain parallel processor
ICS '93 Proceedings of the 7th international conference on Supercomputing
Dynamic switching of coherent cache protocols and its effects on Doacross loops
ICS '93 Proceedings of the 7th international conference on Supercomputing
Request Combining in Multiprocessors with Arbitrary Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Dataflow computer development in Japan
ICS '90 Proceedings of the 4th international conference on Supercomputing
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Evon: an extended von Neumann model for parallel processing
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
The Hughes Data Flow Multiprocessor: architecture for efficient signal and data processing
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
IEEE Transactions on Parallel and Distributed Systems
NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems
IEEE Transactions on Parallel and Distributed Systems
Two Fundamental Limits on Dataflow Multiprocessing
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Connection principles for multipath, packet switching networks
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Rapid Prototyping of Networks of Asynchronous Multiple Functional Units
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
The digital divide of computing
Proceedings of the 1st conference on Computing frontiers
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
WSEAS Transactions on Computers
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In recent years, there have been many attempts to construct multiple-processor computer systems. The majority of these systems are based on von Neumann style uniprocessors. To exploit the parallelism in algorithms, any high performance multiprocessor system must, however, address two very basic issues-the ability to tolerate long latencies for memory requests and the ability to achieve unconstrained, yet synchronized, access to shared data. In this paper, we define these two problems, and examine the ways in which they are addressed by some of the current and past von Neumann multiprocessor projects. We then proceed to hypothesize that the problems cannot be solved in a von Neumann context. We offer the data flow model as one possible alternative, and we describe our research in this area.