Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
URPR—An extension of URCR for software pipelining
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A technique for reducing synchronization overhead in large scale multiprocessors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
A Fortran compiler for the FPS-164 scientific computer
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
Mathematical Theory of Program Correctness
Mathematical Theory of Program Correctness
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
The microprogramming of pipelined processors
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Percolation Scheduling: A Parallel Compilation Technique
Percolation Scheduling: A Parallel Compilation Technique
The optimization of horizontal microcode within and beyond basic blocks: an application of processor scheduling with resources
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We describe a compilation algorithm for efficient software pipelining of general inner loops, where the number of iterations and the time taken by each iteration may be unpredictable, due to arbitrary if-then-else statements and conditional exit statements within the loop. As our target machine, we assume a wide instruction word architecture that allows multi-way branching in the form of if-then-else trees, and that allows conditional register transfers depending on where the microinstruction branches to (a hardware implementation proposal for such a machine is briefly described in the paper). Our compilation algorithm, which we call the pipeline scheduling technique, produces a software-pipelined version of a given inner loop, which allows a new iteration of the loop to begin on every cycle whenever dependences and resources permit. The correctness and termination properties of the algorithm are studied in the paper.