Deterministic Processor Scheduling
ACM Computing Surveys (CSUR)
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
A methodology for programming a pipeline array processor
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Optimization of horizontal microcode generation for loop structures
ICS '88 Proceedings of the 2nd international conference on Supercomputing
An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels
ICS '88 Proceedings of the 2nd international conference on Supercomputing
A compilation technique for software pipelining of loops with conditional jumps
ACM SIGMICRO Newsletter
Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Tradeoffs in instruction format design for horizontal architectures
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Overlapped loop support in the Cydra 5
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
On reordering instruction streams for pipelined computers
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
A study of scalar compilation techniques for pipelined supercomputers
ACM Transactions on Mathematical Software (TOMS)
The floating point performance of a superscalar SPARC processor
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
A new technique for induction variable removal
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Register requirements of pipelined processors
ICS '92 Proceedings of the 6th international conference on Supercomputing
Speedup of band linear recurrences in the presence of resource constraints
ICS '92 Proceedings of the 6th international conference on Supercomputing
A non-deterministic scheduler for a software pipelining compiler
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Controlling and sequencing a heavily pipelined floating-point operator
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Microarchitecture support for dynamic scheduling of acyclic task graphs
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
StaCS: a Static Control Superscalar architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
ACM Letters on Programming Languages and Systems (LOPLAS)
Minimum register requirements for a modulo schedule
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
HTGL: a program modelling language
ACM SIGARCH Computer Architecture News
Register allocation for predicated code
Proceedings of the 28th annual international symposium on Microarchitecture
Stage scheduling: a technique to reduce the register requirements of a modulo schedule
Proceedings of the 28th annual international symposium on Microarchitecture
Realistic scheduling: compaction for pipelined architectures
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
An instruction reoderer for pipelined computers
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
An analysis of dynamic scheduling techniques for symbolic applications
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
From algorithm parallelism to instruction-level parallelism: an encode-decode chain using prefix-sum
Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures
Vector register design for polycyclic vector scheduling
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
ACM SIGPLAN Notices
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Evaluating the Use of Register Queues in Software Pipelined Loops
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Conflict-Free Access to Multiple Single-Ported Register Files
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Improved instruction formation in the exhaustive local microcode compaction algorithm
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Probabilistic Predicate-Aware Modulo Scheduling
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Facilitating compiler optimizations through the dynamic mapping of alternate register structures
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
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A horizontal architecture consists of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. Such architectures offer the potential for high performance scientific computing at a modest cost. If this potential performance is to be realized, the multiple resources of a horizontal processor must be scheduled effectively. The scheduling task for conventional horizontal processors is quite complex and the construction of highly optimizing compilers for them is a difficult and expensive project. The polycyclic architecture is a horizontal architecture with architectural support for the scheduling task. The complexity of scheduling conventional horizontal processors and the ease of scheduling polycyclic processors is demonstrated by means of an example.