Highly concurrent scalar processing
Highly concurrent scalar processing
HPS, a new microarchitecture: rationale and introduction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
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ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
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Performance bounds and buffer space requirements for concurrent processors
Performance bounds and buffer space requirements for concurrent processors
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ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
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ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
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A systolic array optimizing compiler
Minimum register requirements for a modulo schedule
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
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Proceedings of the 28th annual international symposium on Microarchitecture
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Hypernode reduction modulo scheduling
Proceedings of the 28th annual international symposium on Microarchitecture
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ICS '97 Proceedings of the 11th international conference on Supercomputing
Modulo Scheduling with Reduced Register Pressure
IEEE Transactions on Computers
Quantitative Evaluation of Register Pressure on Software Pipelined Loops
International Journal of Parallel Programming
Effective cluster assignment for modulo scheduling
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Improved spill code generation for software pipelined loops
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Lifetime-Sensitive Modulo Scheduling in a Production Environment
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Journal of VLSI Signal Processing Systems
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
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Non-Consistent Dual Register Files to Reduce Register Pressure
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Register Constrained Modulo Scheduling
IEEE Transactions on Parallel and Distributed Systems
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EURASIP Journal on Applied Signal Processing
On Periodic Register Need in Software Pipelining
IEEE Transactions on Computers
MIRS: modulo scheduling with integrated register spilling
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
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To enable concurrent instruction execution, scientific computers generally rely on pipelining, which combines with faster system clocks to achieve greater throughput. Each concurrently executing instruction requires buffer space, usually implemented as a register, to receive its result. This paper focuses on the issue of how many registers are required to achieve optimal performance in pipelined scientific computers. Four machine models are considered: single, double, and triple issue scalar machines, and vector machines with various register lengths. A model is presented that accurately relates the register requirements for optimum performance cyclically scheduled loops with tree-dependence graphs to the degree of function unit pipelining, the instruction issue bandwidth, and code properties. A method for finding upper and lower bounds on the minimum register requirements is also presented.The result of this work is a theory for assessing register requirements that can be used to reveal fundamental differences among machines within a space of architectural and implementation design choices. Some experimental data is also provided to support the theory.