The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A case study in using two-level control stores
ACM SIGMICRO Newsletter
Software and hardware parallelism on the iWarp multi-computer
ICS '91 Proceedings of the 5th international conference on Supercomputing
Mapping concurrent programs to VLIW processors
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
GURPR*: a new global software pipelining algorithm
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Analysis of free schedule in periodic graphs
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Register requirements of pipelined processors
ICS '92 Proceedings of the 6th international conference on Supercomputing
A non-deterministic scheduler for a software pipelining compiler
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Controlling and sequencing a heavily pipelined floating-point operator
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A VLIW architecture for optimal execution of branch-intensive loops
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Enhanced modulo scheduling for loops with conditional branches
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
StaCS: a Static Control Superscalar architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
ACM Computing Surveys (CSUR)
Resource-Constrained Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
GPMB—software pipelining branch-intensive loops
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Software pipelining: a comparison and improvement
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A case study in using two-level control stores
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Vector register design for polycyclic vector scheduling
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors
Proceedings of the ninth international symposium on Hardware/software codesign
Automatic data and computation decomposition on distributed memory parallel computers
ACM Transactions on Programming Languages and Systems (TOPLAS)
CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Compiling for Distributed Memory Architectures
IEEE Transactions on Parallel and Distributed Systems
Trace Software Pipelining: A Novel Technique for Parallelization of Loops with Branches
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Improving Hash Join Performance through Prefetching
ICDE '04 Proceedings of the 20th International Conference on Data Engineering
Software pipelining: an effective scheduling technique for VLIW machines
ACM SIGPLAN Notices - Best of PLDI 1979-1999
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Differential register allocation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Improving hash join performance through prefetching
ACM Transactions on Database Systems (TODS)
Resource aware mapping on coarse grained reconfigurable arrays
Microprocessors & Microsystems
Paper: A boltzmann machine approach to code optimization
Parallel Computing
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