Compilation for a high-performance systolic array
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Warp architecture and implementation
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A customized control store design in microprogrammed control units
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
General microprogram width reduction using generator sets
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
A systolic array optimizing compiler
A systolic array optimizing compiler
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A two-level control store can reduce storage requirements of microprograms without affecting microprogrammability, which is important for a processor programmed directly in microcode. This paper presents a case study investigating how to use a two-level control store effectively. The study is based on Warp cell, a high-performance, microprogrammable processor used in a systolic array computer called Warp. Warp cell is programmed directly in microcode by an optimizing compiler and uses wide horizontal microinstructions with over 200 bits.Two methods which can increase the effectiveness of using a two-level control store have been considered. First, control store configuration can be adjusted so that the storage of an instruction can be partitioned among microstore and one or more nanostores to maximize storage efficiency. Second, it is possible to increase storage reduction of microprograms by exploiting insignificant and symmetric fields in instructions in mapping microprograms to the control store. It has been found that the average storage reduction for Warp cell programs can be increased from 41% in a straightforward two-level control store implementation to 72% by using these methods.