Warp architecture and implementation

Authors:
M. Annaratone;E. Arnould;T. Gross;H. T. Kung;M. S. Lam
Affiliations:
Department of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania
Venue:
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Year:
1986

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Abstract

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.