Communications of the ACM - Special section on computer architecture
Warp architecture and implementation
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Low-level vision on warp and the apply programming model
Parallel computation and computers for artificial intelligence
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Architecture and compiler tradeoffs for a long instruction wordprocessor
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Communication in iWarp systems
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The NuMesh: a modular, scalable communications substrate
ICS '93 Proceedings of the 7th international conference on Supercomputing
Adaptive Fault-Tolerant Deadlock-Free Routing in Meshes and Hypercubes
IEEE Transactions on Computers
A Cost and Speed Model for k-ary n-Cube Wormhole Routers
IEEE Transactions on Parallel and Distributed Systems
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic
IEEE Transactions on Computers
A simple mathematical model of adaptive routing in wormhole k-ary n-cubes
Proceedings of the 2002 ACM symposium on Applied computing
A Comparative Study of Switching Methods in Multicomputer Networks
The Journal of Supercomputing
On the merits of hypermeshes and tori with adaptive routing
Journal of Systems Architecture: the EUROMICRO Journal
Multiprocessor Raster Plotting
IEEE Computer Graphics and Applications
A Fine-Grain Threaded Abstract Machine
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
A Performance Model of Adaptive Routing in k-Ary n-Cubes with Matrix-Transpose Traffic
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Analytical modelling of wormhole-routed k-ary n-cubes in the presence of matrix-transpose traffic
Journal of Parallel and Distributed Computing
Higher dimensional hexagonal networks
Journal of Parallel and Distributed Computing
The Effect of Virtual Channel Organization on the Performance of Interconnection Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Analytical Modelling of Hot-Spot Traffic in Deterministically-Routed K-Ary N-Cubes
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 15 - Volume 16
Comparative Modeling of Network Topologies and Routing Strategies in Multicomputers
International Journal of High Performance Computing Applications
Switch fabric design for high performance IP routers: a survey
Journal of Systems Architecture: the EUROMICRO Journal
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 2
An efficient non-contiguous processor allocation strategy for 2D mesh connected multicomputers
Information Sciences: an International Journal
Communication delay analysis of fault-tolerant pipelined circuit switching in torus
Journal of Computer and System Sciences
Pipelined circuit switching: Analysis for the torus with non-uniform traffic
Journal of Systems Architecture: the EUROMICRO Journal
Combinatorial performance modelling of toroidal cubes
Journal of Systems Architecture: the EUROMICRO Journal
Parallel Lagrange interpolation on k-ary n-cubes with maximum channel utilization
The Journal of Supercomputing
Comparative evaluation of contiguous allocation strategies on 3D mesh multicomputers
Journal of Systems and Software
Future Generation Computer Systems
Path embeddings in faulty 3-ary n-cubes
Information Sciences: an International Journal
Resource placement in three-dimensional tori
Parallel Computing
Matching preclusion for k-ary n-cubes
Discrete Applied Mathematics
Panconnectivity and edge-pancyclicity of k-ary n-cubes with faulty elements
Discrete Applied Mathematics
Edge-bipancyclicity of the k-ary n-cubes with faulty nodes and edges
Information Sciences: an International Journal
Hamiltonian paths and cycles with prescribed edges in the 3-ary n-cube
Information Sciences: an International Journal
Hamiltonian cycles passing through linear forests in k-ary n-cubes
Discrete Applied Mathematics
Performance evaluation of noncontiguous allocation algorithms for 2D mesh interconnection networks
Journal of Systems and Software
Pancyclicity of k-ary n-cube networks with faulty vertices and edges
Discrete Applied Mathematics
Fault tolerance in k-ary n-cube networks
Theoretical Computer Science
A performance comparison of the contiguous allocation strategies in 3D mesh connected multicomputers
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Panconnectivity of n-dimensional torus networks with faulty vertices and edges
Discrete Applied Mathematics
Fault-free Hamiltonian cycles passing through a linear forest in ternary n-cubes with faulty edges
Theoretical Computer Science
Fault-tolerant embedding of cycles of various lengths in k-ary n-cubes
Information and Computation
Strong matching preclusion for k-ary n-cubes
Discrete Applied Mathematics
Hamiltonian path embeddings in conditional faulty k-ary n-cubes
Information Sciences: an International Journal
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An architecture that efficiently supports both message-passing and systolic communications in one system is presented. This architecture incorporates a variety of innovative features unifying both computational power and communications flexibility in one VLSI component, the iWarp microprocessor. The message-based communication model is discussed, and an overview of the architecture is given. Two principle iWarp components, called the communication agent and the computation agent, and the register file they share are described. The efficiencies of word-level communication are examined. The software development environment is also described.