Communications of the ACM - Special section on computer architecture
Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
Performance of unbuffered shuffle-exchange networks
IEEE Transactions on Computers - The MIT Press scientific computation series
The Load-Sharing Banyan Network
IEEE Transactions on Computers
Computer
Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Realizing Fault-Tolerant Interconnection Networks Via Chaining
IEEE Transactions on Computers - Fault-Tolerant Computing
The iPSC/2 direct-connect communications technology
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Using feedback to control tree saturation in multistage interconnection networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Nonuniform traffic spots (NUTS) in multistage interconnection networks
Journal of Parallel and Distributed Computing
Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
Alleviating the impact of tree saturation on multistage interconnection network performance
Journal of Parallel and Distributed Computing - Special issue on shared-memory multiprocessors
The B-Network: A Multistage Interconnection Network with Backward Links
IEEE Transactions on Computers
Performance of a crosspoint buffered ATM switch fabric
IEEE INFOCOM '92 Proceedings of the eleventh annual joint conference of the IEEE computer and communications societies on One world through communications (Vol. 1)
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
“Hypermeshes”: optical interconnection networks for parallel computing
Journal of Parallel and Distributed Computing
Using a Multipath Network for Reducing the Effects of Hot Spots
IEEE Transactions on Parallel and Distributed Systems
Survey of ATM switch architectures
Computer Networks and ISDN Systems
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Interconnection network analysis for a compliant massively parallel processor
Journal of Systems Architecture: the EUROMICRO Journal
On the relative performance merits of hypercube and hypermesh networks
Journal of Systems Architecture: the EUROMICRO Journal
Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages
IEEE Transactions on Computers
An Analytical Model of Adaptive Wormhole Routing in Hypercubes in the Presence of Hot Spot Traffic
IEEE Transactions on Parallel and Distributed Systems
ACM SIGARCH Computer Architecture News
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic
IEEE Transactions on Computers
Asynchronous Transfer Mode Networks: Performance Issues
Asynchronous Transfer Mode Networks: Performance Issues
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
On the merits of hypermeshes and tori with adaptive routing
Journal of Systems Architecture: the EUROMICRO Journal
The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control
IEEE Transactions on Parallel and Distributed Systems
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Minimal Adaptive Wormhole Routing with Time-Dependent Deadlock Recovery
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Optimal Topology for Distributed Shared-Memory Multiprocessors: Hypercubes Again?
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing - Volume I
Performance Evaluation of Crossbar Switch Fabrics in Core Routers
AINA '03 Proceedings of the 17th International Conference on Advanced Information Networking and Applications
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
SPDP '95 Proceedings of the 7th IEEE Symposium on Parallel and Distributeed Processing
Performance Analysis of a Multicast Switch Based on Multistage Interconnection Networks
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Adaptive routing in k-ary n-cube multicomputers
ICPADS '96 Proceedings of the 1996 International Conference on Parallel and Distributed Systems
ISPAN '00 Proceedings of the 2000 International Symposium on Parallel Architectures, Algorithms and Networks
On the Speedup Required for Combined Input and Output Queued Switching
On the Speedup Required for Combined Input and Output Queued Switching
Multistage-Based Switching Fabrics for Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router
Journal of Systems Architecture: the EUROMICRO Journal
Comparative Modeling of Network Topologies and Routing Strategies in Multicomputers
International Journal of High Performance Computing Applications
Interconnection network front-end controller combining to reduce hot spots effects
Computer Communications
Multicast scheduling for input-queued switches
IEEE Journal on Selected Areas in Communications
Performance issues in VC-merge capable switches for multiprotocol label switching
IEEE Journal on Selected Areas in Communications
Architectural designs for a scalable reconfigurable IP router
Journal of Systems Architecture: the EUROMICRO Journal
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Traditionally, besides vendor product descriptions on high performance Internet Protocol (IP) router hardware (HW) architectures, materials on this subject area seldom appear in research literature. Recently, we introduced an architectural concept of HW scalability and bi-directional HW reconfigurability for high performance IP touters. Application of these two conceptual attributes enables router HW flexibility to adapt to today's IP network environment with rapid changes in capacity and traffic characteristics. We analyzed 10 switch fabrics (SFs), selected and also presented brief survey of HW architectural techniques that enable the attributes for three candidates that can serve such a router. In this paper, we present a full survey of these 10 SFs. The intention is to provide background reference material on an area not yet frequently visited in formal literature.