Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
Routing, merging, and sorting on parallel models of computation
Journal of Computer and System Sciences
The connection machine
High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The architecture and programming of the Ametek series 2010 multicomputer
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
A framework for adaptive routing in multicomputer networks
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Tight bounds for oblivious routing in the hypercube
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Adaptive, minimal routing in hypercubes
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Fully-adaptive minimal deadlock-free packet routing in hypercubes, meshes, and other networks
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Chaos router: architecture and performance
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Deterministic and chaotic adaptive routing in multicomputers
Deterministic and chaotic adaptive routing in multicomputers
Requirements for deadlock-free, adaptive packet routing
PODC '92 Proceedings of the eleventh annual ACM symposium on Principles of distributed computing
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Chaotic routing: design and implementation of an adaptive multicomputer network router
Chaotic routing: design and implementation of an adaptive multicomputer network router
The chaos router chip: design and implementation of an adaptive router
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Universal schemes for parallel communication
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Circuit-switched multicomputers and heuristic load placement
Circuit-switched multicomputers and heuristic load placement
ROMM routing on mesh and torus networks
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
IEEE Transactions on Parallel and Distributed Systems
Using ZPL to develop a parallel chaos router simulator
WSC '96 Proceedings of the 28th conference on Winter simulation
Triplex: a multi-class routing algorithm
Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures
A Router Architecture for Flexible Routing and Switching in Multihop Point-To-Point Networks
IEEE Transactions on Parallel and Distributed Systems
A Testbed for Evaluation of Fault-Tolerant Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Wait-Free Deflection Routing of Long Messages
IEEE Transactions on Parallel and Distributed Systems
A new routing mechanism for networks with irregular topology
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
MediaWorm: A QoS Capable Router Architecture for Clusters
IEEE Transactions on Parallel and Distributed Systems
A New Communication Mechanism for Cluster Computing
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Networks on which hot-potato routing does not livelock
Distributed Computing
In-Order Packet Delivery in Interconnection Networks using Adaptive Routing
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Switch fabric design for high performance IP routers: a survey
Journal of Systems Architecture: the EUROMICRO Journal
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Routing to support communication in dependable networks
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
A low-latency modular switch for CMP systems
Microprocessors & Microsystems
PaCT'05 Proceedings of the 8th international conference on Parallel Computing Technologies
A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems
Journal of Parallel and Distributed Computing
| Hi-index | 14.98 |
The Chaos router, a randomizing, nonminimal adaptive packet router is introduced. Adaptive routers allow messages to dynamically select paths, depending on network traffic, and bypass congested nodes. This flexibility contrasts with oblivious packet routers where the path of a packet is statically determined at the source node. A key advancement of the Chaos router over previous nonminimal routers is the use of randomization to eliminate the need for livelock protection. This simplifies adaptive routing to be of approximately the same complexity along the critical decision path as an oblivious router. The primary cost is that the Chaos router is probabilistically livelock free rather than being deterministically livelock free, but evidence is presented implying that these are equivalent in practice. The principal advantage is excellent performance for nonuniform traffic patterns. The Chaos router is described, it is shown to be deadlock free and probabilistically livelock free, and performance results are presented for a variety of work loads.